Software-based Testing of Sequential VHDL Descriptions

In this paper, we propose a new high-level test pattern generation technique for sequential circuits. The main motivation is two-fold: on one hand, we elaborate test data for design validation; on the other hand, we deal with the problem of structural test development at functional level. The proposed test method, i.e. mutation testing, allows us to work with a fault model at software level on VHDL descriptions; this approach has already shown its efficiency on combinational descriptions. In order to tackle the specific problem of sequential circuits, the description is modified so that the state variables are made observable and controllable.